The present invention relates to a digital video system such as a multi media system, a digital video, a digital video disk (DVD), a video-CD, a digital VCR, a digital television, a camcorder and a video editor, and more particularly, to a digital video encoder in a digital video system.
A digital video decoder in a digital video system reads compressed data from a storage medium and decodes it to thus output a decoded digital video signal. In a digital video encoder, the decoded digital video signal is input, and divided into chrominance and luminance signals. The divided signals are converted to an analogue composite video baseband signal (CVBS) in response to a clock, a vertical synchronizing signal, a horizontal synchronizing signal, and a field signal. This CVBS has analogue video data and is transmitted to a display device such as a CRT.
In a conventional digital video encoder of a digital video system, a main clock is generated from a signal having 4fsc (Here, fsc is 3.58 MHz in NTSC or 4.43 MHz in PAL). Thus, according to the data communication regulation CCIR (International Radio Consultative Committee) 601 or 656, a standard data sampling clock frequency used in the conventional digital video encoder should be 27 MHz or 13.5 MHz. Thus, when using the conventional digital video encoder, input digital video data is not synchronized with the main clock and thus the data can be damaged.
In particular, when the digital data compressed according to an MPEG standard is restored and displayed, a blocking phenomenon can be generated due to a nonlinear feature of data according to the connection between scanning lines.
Also, when compressing the data using the MPEG standard, a high-frequency data component is removed so that a gentle noise, that is, mosquito noise is generated on a display screen when reproducing the compressed data.
Furthermore, since a chip for an on screen display (OSD) and a chip serving as a digital video encoder are separately provided in the prior art, a clock corresponding to each chip should be separately generated and various financial and spacial problems occur when connecting one chip to the other in the case of requesting an OSD and a digital video encoder simultaneously.